Referring to prior art FIG. 1A, a wafer 100 used for fabricating a plurality of die 105 in accordance with the convention art is shown. A desired integrated circuit is typically fabricated on each die 105 on the wafer 100. Integrated circuits typically comprise periphery and core circuitry. For example, the periphery circuitry of a memory device comprises decoder logic, control logic and sense logic. The core circuitry of the memory device comprises an array of memory cells. As depicted in prior art FIG. 1B, each die 105 is typically fabricated to contain the periphery circuitry along the outer periphery region 110 of the die 105, and the core circuitry in the core region 120 of the die 105. The periphery 110 and the core 120 may be separated by an interface region 115. The interface region 115 may also contain isolation regions, circuitry, interconnects, and/or the like.
As semiconductor technology progresses, increasing device density and speed continues to be critical. Increasing density and speed may be achieved by scaling semiconductor devices. Increases in device scaling have resulted in the continued need to improve isolation regions between devices. Improved isolation regions should be narrower and/or deeper. The isolation regions should also have improved electrical insulating qualities.
Prior art FIGS. 2 and 3 illustrate why improving device isolation is required to continue to scale devices. In prior art FIG. 2, there are two device regions separated by a field region. For example, each device region has a transistor formed by a source 210, gate 220, and drain 230. Each device region encompasses the depletion regions resulting from the reverse-biased source-substrate and drain-substrate junctions. As long as the separation between the devices is greater than twice the maximum depletion layer width 240, isolation is maintained. However, for advanced processes with deep sub-micron feature sizes, this form of isolation prohibits sufficient scaling.
Prior art FIG. 3 illustrates a shallow trench isolation (STI) structure, which is currently used to provide isolation between devices. Shallow trench isolation allows further scaling and increased circuit density. For shallow trench isolation, the device region is masked, a trench is etched 350, and then the trench is filled with a dielectric 360, such as tetraethylorthosilicate (TEOS) formed oxide. A transistor having a source 310, gate 320, and drain 330 are formed between the shallow trench isolation regions. The dielectric 360 filled shallow trench 350 effectively cuts off and separates the depletion layers 340 of adjacent transistors, thus allowing the devices to be fabricated closer together.
Typically, the circuitry in the periphery region is fabricated with a lower component density than circuitry in the core region. Furthermore, the circuitry in the periphery region typically operates at a higher voltage level than circuitry in the core region. As a result, the trenches in the periphery region should be relatively deep. However, the relatively low circuit density allows for wide trenches. Thus, relatively large aspect ratio (depth of trench divided by width of trench) trenches are typically utilized in the periphery region.
On the other hand, the trenches can be relatively shallow in the core region. However, to achieve high circuit density, sufficiently narrow trenches are utilized. Thus, relatively small aspect ratio trenches are typically utilized in the core region. However, the minimum usable aspect ratio is limited by the ability to fill the trench with a dielectric. For example, when the aspect ratio of trenches is less than approximately 7.5 it is difficult to deposit dielectric material having uniform density in such trenches.
Furthermore, current trench forming techniques typically result in trenches having sharp corners. As the geometry of the trenches has continued to shrink, the sharp corners of the trenches suffer from corner effects, which can degrade performance in and/or cause failure of the integrated circuit. For example, an electric potential present across an isolation region produces a high electric field per unit area at the corners of the trench. Such a high electric field can produce leakage current or even oxide layer breakdown.
Accordingly, there is a continued need for improving the device isolation regions in integrated circuits having multiple trench isolation regions. What is needed is a means for depositing a trench fill having a uniform density in small aspect ratio device isolation trenches. Furthermore, the device isolation method should be adapted to reduce corner effects, such as leakage current, and the like. Embodiments of the present invention provide a novel solution to the above needs.